1. Field of the Invention
The present invention relates generally to the manufacturing of integrated circuits (ICs), and particularly to the seed layers in damascene and dual damascene processes, gate metals of thin film transistors and capacitor electrodes in ICs.
More particularly the present invention relates to a method of depositing seed layers for a damascene and dual damascene structures, gate metals of thin film transistors and capacitor electrodes in ICs by an atomic layer deposition (ALD) method.
2. Description of the Related Art
The atomic layer deposition (ALD) method of depositing thin films has several attractive features including excellent step coverage, even on large areas, and a dense and pinhole-free structure. Therefore, it is of great interest to apply ALD to the deposition of metallization layers of advanced integrated circuits (ICs), where the continuously increasing packing density and aspect ratio set higher and higher demands upon the metallization layers. Applications where high quality metallization is particularly needed are dual damascene structures, gates in transistors and capacitors in ICs. However, due to the fact that ALD is based on sequential self-saturating surface reactions of source chemical compounds, depositing high quality elemental metal thin films by ALD is very difficult.
In ALD, the source chemical molecules chemisorb on the substrate via active sites on the substrate surface. Typical active sites for metal source chemicals are —OH, —NH2 and >NH groups. Metal-oxygen-metal bridges on the surface may also act as active sites. When a metal source chemical molecule reacts with the active site, a strong bond is formed between the surface and the ligand of the source chemical molecule is simultaneously released as a by-product.
In ALD, films grow with a constant growth rate. Each deposition cycle produces one molecular layer of the deposited material on the substrate surface. Usually the growth rate is well below one molecular layer/cycle because the adsorbed source chemical molecules may be bulky or because substrate temperature affects the number of active sites (e.g. —OH groups) on the surface. It is well known that metal oxide thin films produced by ALD are uniform, have excellent adhesion and thus are firmly bonded to the substrate surface.
Experiments have revealed a drawback of the growth of metal thin films by an ALD type method. In the case of metal deposition it is difficult to attach source chemical molecules to the surface because essentially no active sites exist on the surface. The metal film grown is often non-uniform over an area of the substrate and it is easily peeled off from the surface, which indicates very poor adhesion of the film to the substrate.
Several attempts have been made to produce metal thin films by ALD type methods. Reproducibility of such an ALD metal growth process has traditionally been poor and the reactions do not take place at all on insulating surfaces like silicon oxide. There are publications about the ALD deposition of Cu metal by pulsing a copper compound, e.g. Cu(thd)2, on a surface and then reducing the Cu(thd)2 molecules bound to the surface into Cu with H2.
R. Solanki et al. (Electrochemical and Solid-State Letters 3 (2000) 479-480) have deposited copper seed layers by ALD. They deposited copper directly from alternate pulses of bis(1,1,1,5,5,5-hexafluoroacetylacetonato)copper(II)hydrate and either methanol, ethanol or formalin, i.e. a water solution of formaldehyde. The total pulsing cycle time was 64 s, i.e. slightly over one minute. Although the growth rate was not mentioned in the publication, a typical growth rate of a thin film made by ALD from metal β-diketonates is 0.03 nm/cycle due to the steric hindrance of the source chemical molecules. Thus, the deposition time for a 10 nm copper seed layer would be over 5 hours, which is uneconomical for wafer processing. A required minimum throughput of a wafer reactor is 10-12wafers/hour. It is to be noted that according to Strem Chemicals, Inc. the decomposition temperature of the copper compound used by R. Solanki et al. is 220° C. R. Solanki et al. noticed copper film growth when the substrate temperature was 230-300° C. Therefore, partial thermal decomposition of copper source compound on substrate surface is probable.
One of the most advanced IC structures is the dual damascene structure which consists of a silicon substrate with transistors (source, gate and drain). Several electrically conducting layers are needed in the structure. The first metallization level is done with tungsten plugs and aluminium interconnects to prevent the contamination of the gate with copper. The remainder of the metallization levels are made of copper.
The process steps of a dual damascene process are described below.
Step 1. A silicon nitride etch stop is grown on the previous metallization surface.
Step 2. A via level dielectric is deposited.
Step 3. Another silicon nitride etch stop is deposited.
Step 4. A trench level dielectric is deposited. SiO2 has been favoured as the dielectric material. Low-k materials such as nitrided silicon oxide and polymers have been experimented with as an alternative dielectric material.
Step 5. Patterning of dielectric by photolithography.                a. A resist layer is deposited on dielectrics surface.        b. The resist layer is patterned and the resist is removed from the via areas.        c. Dielectrics are etched from the via areas with directional plasma. Etching terminates at the silicon nitride surface.        d. Resist is stripped from the surface.        
Step 6. Patterning of the etch stop layer by photolithography.                e. A second resist layer is deposited on the surface.        f. The resist layer is patterned and it is removed from the trench areas.        g. Silicon nitride is removed with a short plasma nitride etch from the bottom of the holes that were made with the first plasma oxide etch.        h. The second plasma oxide etch removes silicon dioxide from the exposed via and trench areas until the first silicon nitride etch stop is reached.        i. The first silicon nitride etch stop is removed from the via bottom and the second silicon nitride etch stop from the trench bottom with a short plasma nitride etch.        j. The resist is stripped from the substrate.        
Step 7. A diffusion barrier layer is grown on all exposed surfaces.
Step 8. A seed layer for copper deposition is grown with CVD or PVD on the diffusion barrier layer.
Step 9. Vias and trenches are filled with copper by an electroplating process.
Step 10. The substrate surface is planarized with chemical mechanical polishing (CMP). The surface is polished until copper and a barrier layer are left only in trenches and vias.
Step 11. The surface is capped with a silicon nitride etch stop layer.
Step 12. The metallization process is then repeated for all the remaining metallization levels.
Alternatives for copper electroplating (Step 9) are electroless plating, physical vapor deposition (PVD) and chemical vapor deposition (CVD). A seed layer (c.f. Step 8) is only needed for the electroplating process. Traditionally such a seed layer is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In the electroplating process the substrate having an electrically conductive seed layer is immersed in a metal compound solution. The electrically conductive surface of the substrate is connected to an external DC power supply. A current passes through the substrate surface into the solution and metal is deposited on the substrate. The seed layer has high conductivity and it acts as a conduction and nucleation layer for the electroplating process. One can envision a seed layer that acts as a nucleation layer for the CVD process. The seed layer carries current from the edge of the wafer to the center of the wafer and from the top surface of the wafer into the bottom of vias and trenches. A uniform and continuous seed layer is necessary to get uniform electroplated copper. Electrical contact is made to the seed layer. The quantity of the deposited metal is directly proportional to the local current density on the substrate.
The benefits of copper compared to aluminum are lower resistivity and better resistance to electromigration. Furthermore, since tighter packing density can be obtained with copper, fewer metallization levels are needed and the manufacturing costs are lower than with aluminum. With increasing aspect ratio it is becoming difficult to get sufficient step coverage for the seed layer with the state of the art technology.
In dynamic random access memories (DRAM), capacitors store data bits in the form of electrical charge. These memory capacitors must be recharged frequently due to the leaking of electrons. The simplest capacitor consists of two parallel metallic plates separated with a dielectric material. The capacity (C) of this plate capacitor depends according to equation (I) on the area (A) of the metallic plate, the distance (d) between the metallic plates and the dielectric constant (k) of the dielectric material. ε0 is the permittivity of space.C=kε0A/d  (I)
Cylindrical capacitors are often used. The conductors are arranged coaxially. The charge resides on the inner wall of the outer conductor and on the outer surface of the inner conductor. In this case the capacitance (C) depends on the radius of the outer surface of the inner conductor (a), radius of the inner surface of the outer conductor (b), length of the cylinder (l) and dielectric constant (k) of the dielectric material between the conductors as shown in equation (II).C=2πkε0l/ln(b/a)  (II)
The feature sizes in DRAMs are decreasing continuously. The capacitors must be made smaller in successive DRAM generation. In order to save surface area, planar capacitors are being replaced with vertical coaxial capacitors that may have aggressive aspect ratios. Decreasing the charge storing area means that the distance between the conductors must be decreased and/or the dielectric constant of the dielectric must be increased in order to keep the capacity sufficient. Decreasing the distance between the conductors causes voltage breakdown when the insulator thickness is too thin to hold the voltage.
Using high-k dielectrics, such as TiO2 and Ta2O5, resolves the above described problem related to decreasing feature size. However, high-k dielectrics create new problems, since they donate oxygen to the conductor and thus the capacitor properties deteriorate. Therefore, inert metals, such as platinum group metals, or conductive metal oxides, such as RuO2, must be used adjacent to the high-k metal oxides. But it is difficult to deposit thin films with good step coverage on new capacitor structures with small feature size and aggressive aspect ratio. As a conclusion, there is an increasing need for a method of producing conductive thin films with good step coverage and excellent thin properties such as adhesion to the substrate.
S.-J. Won et al. have presented a metal-insulator-metal (MIM) capacitor structure for giga-bit DRAMs (Technical Digest of the 2000 International Electron Devices Meeting (IDEM), San Francisco, Calif., Dec. 10-13, 2000). They used Ta2O5 as an insulator while the electrodes consisted of ruthenium which was deposited by CVD from Ru(EtCp)2 gaseous oxygen at 300-400° C. Problems related to the method included poor step coverage and reaction speed sensitivity. When the nodes were made with 0.08 μm design rules, the step coverage dropped to 60%. The reaction of Ru(EtCp)2 with O2 was adversely affected by the partial pressures of the said compounds.
N+ or p+ doped polycrystalline silicon has been used as a gate electrode for transistors. However, several problems are associated with the use of poly-Si gate electrodes. In the case of boron doped p+ poly-Si, the diffusion of boron through the gate SiO2 destroys the electrical properties of the transistor. Poly-Si is thermodynamically unstable against high dielectric constant materials at high processing temperatures. In addition, poly-Si has rather high resistivity compared to metals. There is a tendency to replace the SiO2 gate oxide with a high dielectric constant metal oxide. A metal with appropriate work function would enable the tailoring of the CMOS threshold voltage. Refractory metals have been suggested for gate metals but the stability of the metal-gate oxide interface has been an issue. Platinum group metals are potential candidates for gate metals due to their inert nature. However, appropriate methods of depositing high-quality platinum group metal thin films for gate electrode applications have not yet been developed.
M. Utriainen et al. have demonstrated (Appl. Surf. Sci. 157 (2000) pp. 151-158) that ALD grown metal oxides can be used as interconnects in ICs after reducing the metal oxides into metals. They studied the direct ALD deposition of Cu, Ni and Pt and the indirect Ni growth method via reduction of NiO. However, they had problems with the quality of the nickel film: pinholes were formed on the thin films during the reduction of NiO with hydrogen gas.